As is known in the art, network devices, such as routers and switches, can include network processors to facilitate receiving and transmitting data. In certain network processors, such as IXP Network Processors by Intel Corporation, high-speed queuing and FIFO (First In First Out) structures are supported by a descriptor structure that utilizes pointers to memory. U.S. Patent Application Publication No. US 2003/0140196 A1 discloses exemplary queue control data structures. Packet descriptors that are addressed by pointer structures may be 32-bits or less, for example.
In some known network processors, an operation that involves a read followed by write could result in loss of memory interface cycles. A read-modify-write (RMW) command enters a main command queue or FIFO (First In/First Out) 10 and is subsequently broken up into its constituent read and write commands. The read command is put into a read command FIFO and the write command is put into a write command FIFO. The queued write command must wait for the corresponding read command to finish before the required write data can be formed. If there is a backlog in the read command FIFO, the write FIFO stalls even if there is another write command pending in the write command FIFO that can execute. As a result write cycles are lost on the pin interface.
Similarly if there is a read that is ordered to a write location but write data has not yet been read from the source of the write data, the read can not proceed resulting in wasted read cycles. A similar loss of performance occurs when dealing with SRAM (static random access memory) ring commands.